News - ASUS motherboards to boast full SATA Express performance

[kalniel]

intel is pushing its own propriety tech . again.

It's a defined specification, created by SATA IO, a non-profit organisation currently made up of members from:

Dell Computer Corporation
Hewlett Packard Corporation
HGST
Intel Corporation
Marvell Semiconductor
PMC-Sierra Inc.
SanDisk Corporation
Seagate Technology
Western Digital Corporation

[watercooled]

Oops I missed the post immediately before mine, although I don't really disagree with it TBH. I think it has its place as a transition technology, but ultimately it's just giving you PCIe access over a backwards-compatible port.

@Corky34: You can indeed get native PCIe drives. M.2 essentially uses the SATA express interface which as we've seen offers SATA3 and PCIe. As I briefly covered above though, there are potential compatibility issues with native PCIe drives, but I'd expect that to affect mainly older systems.

@HalloweenJack: There's nothing Intel-proprietary about SATA express.

[LenMargaux]

Not only Asus, but Gigabyte and ASRock as well
http://thepcenthusiast.com/gigabyte-ga-z97x-ud7-th-thunderbolt2/

By the way can you use the SATA Express port as a regular SATA port? Since 1 SATA xpress port looks like it has 2 regular SATA ports and a mini one.
Asus mentioned "so fast that a 10GB full-length HD movie transfers in around 10 seconds" - is this using a regular 7200RPM HDD or an SSD?

[watercooled]

Yeah you can use the two SATA ports, as SATA ports. A SATA express connector will use all three.

The transfer would be for something able to meet that sort of transfer speed, which a HDD isn't going to do any time soon.

[HalloweenJack]

no I meant that I read that intel wanted to support another standard first over sata express

[watercooled]

I don't recall reading anything along those lines?

[Corky34]

@Corky34: You can indeed get native PCIe drives. M.2 essentially uses the SATA express interface which as we've seen offers SATA3 and PCIe. As I briefly covered above though, there are potential compatibility issues with native PCIe drives, but I'd expect that to affect mainly older systems.

Yes you can get PCIe drives, what i meant to say (perhaps badly) is you can't just connect a drive directly to a PCI-e lane. I.e Even PCIe drives have a chip on them that is needed to translate one protocol, or signal type to another. Essentially both SATAe and M.2 do the same thing, exposes one or more PCIe lanes to the drive, they just go about it slightly differently with different connectors.

no I meant that I read that intel wanted to support another standard first over sata express

AFAIK Intel is not going to support SATAe, instead preferring to offer a M.2 drive connector, and SATA III ports.

[watercooled]

Yes you can get PCIe drives, what i meant to say (perhaps badly) is you can't just connect a drive directly to a PCI-e lane. I.e Even PCIe drives have a chip on them that is needed to translate one protocol, or signal type to another. Essentially both SATAe and M.2 do the same thing, exposes one or more PCIe lanes to the drive, they just go about it slightly differently with different connectors.

Nope, I understood what you said. You can get *native* PCIe drives, with no SATA abstraction. Hence the BIOS/compatibility thing I keep mentioning. For example:

http://www.marvell.com/storage/syste...sd-controller/
http://uk.hardware.info/reviews/5199...or-desktop-pcs

[Corky34]

Nope, I understood what you said. You can get *native* PCIe drives, with no SATA abstraction. Hence the BIOS/compatibility thing I keep mentioning. For example:

Maybe the confusion is coming from the term *native* as the examples given still use a form of abstraction, so are not native in the strict definition of the term.
Yes it may not be SATA abstraction but they are still converting one protocol to another.

[watercooled]

Did you read them? Look at the diagram on the Marvell website. It goes PCIe>controller>NAND. There is no abstraction layer. They are native PCIe SSD controllers. Heck, look at the product name!

88NV9145 - NATIVE PCIe SSD CONTROLLER

Or are you just winding me up now since you're now essentially arguing with both a drive manufacturer and a controller manufacturer?

[bert7]

funny that its also on every new z97 gigabyte and asrock board, look close as some are side mounted. what is this place Asus lickers club.

[Corky34]

Did you read them? Look at the diagram on the Marvell website. It goes PCIe>controller>NAND. There is no abstraction layer. They are native PCIe SSD controllers. Heck, look at the product name!

Or are you just winding me up now since you're now essentially arguing with both a drive manufacturer and a controller manufacturer?

Yes i did read them, maybe you need to as well.
The 88NV9145 - NATIVE PCIe SSD CONTROLLER uses a field-programmable gate array (FPGA)
The only difference between a FPGA chip and the normal application-specific integrated circuit (ASIC) is that it is configured by a customer or a designer after manufacturing.

It still uses a integrated circuit (a chip, or a microchip) between the NADS and the PCIe.
If you really believe there is no abstraction layer, please do tell everyone how you think the NAND's talk over the PCIe bus all by them selves.

[kalniel]

funny that its also on every new z97 gigabyte and asrock board, look close as some are side mounted. what is this place Asus lickers club.

No, just the way news sites work - a company like Asus sends you a press release and you report on it. Hexus would do the same from MSI, Gigabyte etc. that's their job.

[watercooled]

Yes i did read them, maybe you need to as well.
The 88NV9145 - NATIVE PCIe SSD CONTROLLER uses a field-programmable gate array (FPGA)
The only difference between a FPGA chip and the normal application-specific integrated circuit (ASIC) is that it is configured by a customer or a designer after manufacturing.

It still uses a integrated circuit (a chip, or a microchip) between the NADS and the PCIe.
If you really believe there is no abstraction layer, please do tell everyone how you think the NAND's talk over the PCIe bus all by them selves.

Learn how to read pal:

Read how the 88NV9145 solves for limitations faced by existing bridge and FPGA-based PCIe SSDs.

I.e. it doesn't use an FPGA. Not that it's even remotely important here. The controller talks directly to the PCIe bus, you know, natively. You can keep moving the goalposts all you want rather than admitting you made a mistake, but you're not fooling anyone. Again, I'm using the definition provided by the manufacturers, feel free to send an email of your disagreement to them. I'm sure they'll file it with all the important business mail.

You mean you want NAND flash memory to talk directly to the PCIe bus? You know you *always* need a NAND controller, right, whether it's via SATA, PCIe or whatever other IO method a device may be using. In certain scenarios this may be embedded on a SOC, but it's still there. You can't just cram NAND right onto an IO bus, in the same way you can't take the platters out of a HDD and shove them into a PCIe slot. Look at a teardown of a SATA SSD, you see that little black square on the PCB? That's the NAND controller.

Maybe contrasting against how first generation PCIe SSDs worked would help you to understand? Essentially, they still used SATA flash controllers and used a SATA controller, possibly in RAID mode, on the card to interface with the PCIe bus.

Note the Sandforce SATA flash controllers next to the NAND banks, and the other controllers to go through the conversion from SATA to PCIe (although a PCI-X step is used here too).
http://www.anandtech.com/show/3788/o...dable-pcie-ssd

I've not at any point said there is no abstraction of the NAND itself because I didn't think anyone claiming to understand how SSDs work would mean that. I clearly said

They are native PCIe SSD controllers.

which they are...

[Corky34]

I.e. it doesn't use an FPGA. Not that it's even remotely important here. The controller talks directly to the PCIe bus, you know, natively. You can keep moving the goalposts all you want rather than admitting you made a mistake, but you're not fooling anyone. Again, I'm using the definition provided by the manufacturers, feel free to send an email of your disagreement to them. I'm sure they'll file it with all the important business mail.

You mean you are being taken in by the marketing BS, it uses an ARM chip that can be configured. It's no different than FPGA or ASIC they are all chips, the only difference is ASIC are designed for specific purposes, and FPGA can be programed by customers or a designer after manufacturing, the ARM chip is the FPGA.

You also claim "There is no abstraction layer" and then actually state "The controller talks directly to the PCIe bus"
This is what is called abstraction, so either it does or it doesn't have an abstraction layer, please make up your mind.

You mean you want NAND flash memory to talk directly to the PCIe bus? You know you *always* need a NAND controller, right, whether it's via SATA, PCIe or whatever other IO method a device may be using. In certain scenarios this may be embedded on a SOC, but it's still there. You can't just cram NAND right onto an IO bus, in the same way you can't take the platters out of a HDD and shove them into a PCIe slot. Look at a teardown of a SATA SSD, you see that little black square on the PCB? That's the NAND controller.

I don't want anything, it was you that claimed "There is no abstraction layer." and said "There are some differences to SATA 'proper' though, like the lack of the abstraction layer"
Maybe you need to look up what an abstraction layer is before claiming there are none.

I've not at any point said there is no abstraction of the NAND itself because I didn't think anyone claiming to understand how SSDs work would mean that. I clearly said

What you clearly said is...

There are some differences to SATA 'proper' though, like the lack of the abstraction layer

And then you bought into the marketing BS, by saying...

@Corky34: You can indeed get native PCIe drives.

Like i said you have been taken in by the marketing BS.

[watercooled]

You don't know what an FPGA is then, it's a functionally different type of chip than either an ASIC or a conventional microprocessor. http://en.wikipedia.org/wiki/Fpga

An ARM chip is a conventional microprocessor, not an FPGA, not by any stretch of the imagination. I've worked with and designed systems around ARM microcontrollers, and FPGAs, so I think I should know the difference,

I was saying there is no extra abstraction layer as there was in previous drives which used SATA NAND controllers behind SATA-PCIe bridges. I don't know how more clear I can make it. You're frankly behaving like a complete troll, arguing with the straw man. I'm not contradicting myself at all. Again, I didn't think anyone claiming to have a basic understanding of how SSDs work would think they could operate without a controller. Clearly I was wrong. Read up on Samsung's SATA NAND controllers, they disclose that they use ARM cores, as I expect a great deal of other HDD and SSD controllers do.

How exactly is it marketing BS by calling an native PCIe NAND controller, a native PCIe NAND controller?

In my 'differences to SATA' quote, I was referring to the differences in implementation; whereas a SATA drive is accessed generally via the standard system BIOS, this is not the case with PCIe drives (yes I'm repeating myself again due to your apparent inability to comprehend textual language), they need their own BIOS to initialise the connection with the system upon boot in order to interface with the operating system kernel. Otherwise, you end up with a non-bootable drive accessible by OS drivers (as was also the case with some earlier PCIe drive implementations IIRC).

Seriously how is a drive that talks directly with PCIe not a native PCIe drive?
Sure the term 'native' can have some ambiguity, but most of the market seem to have agreed upon roughly what it means, which is apparently not like the definition you've puled from somewhere. By your definition, no HDDs/SSDs can be 'native' SATA, IDE, SCSI, SAS, as they all interface with the system via a storage controller.

In this sense, it's generally accepted for the definition of a native drive to be one which does not have unnecessary internal abstraction layers and/or conversion steps. These conversion steps can impact performance, so ideally it's best to do away with them where possible. Or are you now going to argue that nothing can be native, because the electrical signals need to traverse PCB traces and are not part of the CPU fabric? Or is that not enough either because that's really an on-die bus?

Sorry but you're talking total and utter rubbish, have derailed the thread, and have been reported for trolling.

Edit: Lets just go back to your original post, which I replied to:

AFAIK you can't connect any form of drive directly to a PCIe lane, you need something between the two doing the translation.

You can connect a drive to the PCIe bus, which has been proven in the links I provided, with no translation/abstraction between the drive and the PCIe bus. A NAND chip is not a drive, if that's what you're trying to say. NAND+controller=drive. Simple.

You were arguing with JCBeastie's stance on just cutting out SATA as a physical layer and interfacing with PCIe directly, which you said, as far as you knew, wasn't possible. But it is. And has been done. And you can buy it now...