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Thread: The architecture behind AMD's Zen 2 and Ryzen 3000 CPUs

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    Re: The architecture behind AMD's Zen 2 and Ryzen 3000 CPUs

    I have to admit, AMD have really nailed the chip production reuse, I wonder what their failure/recycle rate is and how much of each wafer is consumed. It must be a quite high percentage.

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    Re: The architecture behind AMD's Zen 2 and Ryzen 3000 CPUs

    Quote Originally Posted by Corky34 View Post
    Just to add to this, it seems (Ian Cutress tweet) we're both right:

    That wasn't very clear for me at first but what he's essentially saying is that EPYC uses an I/O die fabricated on 14nm, Ryzen I/O die uses 12nm, and the X570 chipset is actually the I/O die from EPYC, at least i think that's what he's saying, other interpretations are welcomed.
    So they've made the IO die for desktop ryzen in 12nm and 14nm flavours, and have a spare dual channel memory controller on X570? Ian seems to confirm the chipset and IO are on different sizes in the replies to that tweet, so it's not failed parts getting re-used. This seems very odd, but then again I'm not an electrical/electronic engineer.

    Quote Originally Posted by DanceswithUnix View Post
    If that's true... well I wasn't expecting that

    That implies there are wasted memory controllers on the X570 chipset (meh), and more interestingly there are lots of chipset bits already in the CPU. I presume there will be a laptop version that brings those functions out to avoid needing a chipset and save cost and space.
    Ryzen could do that already with the teased 300 "chipset"

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    Re: The architecture behind AMD's Zen 2 and Ryzen 3000 CPUs

    I would imagine they've used a single design for all I/O dies and they thought why not use that for the X570 chipset, it makes a lot of economic and time sense as the EPYC I/O die simply needs two memory controllers disable (or just not connected) for it to be used in Ryzen and simply needs all of them disabled to be used as a chipset, IIRC Zen(+) came with enough connectivity (PCIe, USB, Network, etc) that it didn't need a chipset (southbridge?).

    With Zen2 all that connectivity has been moved out of the CPU core dies and into it's own die, redesigning that just because you need fewer PCIe lane, memory controllers, USB, SATA does seem like a waste of time when you can just churn out the same thing and just not bother using the parts you don't need, it's pretty smart when you think about it.

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