Current gen AMD cooler forward compatibility looks likely

[CAT-THE-FIFTH]

Reading up on the AT article:

Anyway, by these graphics it looks like that for peak single thread, we should see around +8% better than Skylake performance while consuming just over half the power – look for Cinebench R20 scores for one Gracemont thread around 478 then (Skylake 6700K scored 443). With +8% for single thread in mind, the +80% in MT comparing 4 cores of Gracemont to two fully loaded Skylake cores seems a little low – we’ve got double the physical cores with Gracemont compared to Skylake here. But there’s likely some additional performance regression with the cache structure on the new Atom core, which we’ll get to later on this page.

So it seems peak single threaded performance is similar,but some weird funkiness is happening when you use more cores....might be a lack of cache,etc??

[Tabbykatze]

That sounds a likely explanation TBH. It doesn't take much for speculation to take off online these days. I also can't see AMD having separate designs for desktop and server; not just because of having to produce two separate chiplet designs, but also because it would mean two entirely different core complex implementations. I find the latter especially unlikely.

I have to admit, I sat myself on the 12 core bandwagon because it kind of makes sense if Genoa tops out at 96C but if it is actually topping out at 128C then it doesn't so I'll go back to my box!

You might be surprised by the projected performance of the 'small' cores, see link in my previous post.

Yeah, just reading through it now, not sure how I missed one of Mr Cutress' articles!

As an aside, I am interested to see if they really are "as good as Skylake" because if so, then Intel does have some interest edging but it begs the question, this is at ISO frequency (which I presume is locked and matched frequencies) so if they can't clock as high but have the same IPC then they may not be able to go as far as Zen 2.

[watercooled]

Oh I think it needs to be taken in context. The small cores might not be hitting 5GHz but they don't really need too - for their uses, peak single-thread performance is less important and you're well past the point of diminishing returns in terms of power at those sort of clocks. Lots of small(er) cores at moderate clocks could be immensely useful in terms of overall performance and efficiency for highly-threaded applications. Or even to get background tasks off the main cores if the scheduler is advanced enough.

@CAT: Yeah, with all four cores of a cluster maxed out, they could be fighting for cache and memory bandwidth, so a 4 core cluster might not reach the same performance as say a 6600k. But at that stage, the CPU would likely already have 8 big cores loaded, so there are other factors in play anyway.

Personally, I've been interested in the Alder Lake concept for some time now, and I'm really keen to find out how it all pans out in the product.

[CAT-THE-FIFTH]

Actually I think there was a rumour AMD might go the same way after Zen4:
https://videocardz.com/newz/amd-3nm-...g-little-cores
https://hothardware.com/news/amd-pat...zen-8000-zen-5

[Tabbykatze]

Actually I think there was a rumour AMD might go the same way after Zen4:
https://videocardz.com/newz/amd-3nm-...g-little-cores
https://hothardware.com/news/amd-pat...zen-8000-zen-5

I remember those articles, quite an interesting patent, I would like to know more how it'll compare as a hardware level thread manager versus Intels software (seemingly) level thread management.

[watercooled]

On the face of it, it does make a lot of sense when you start getting to high core counts, when considering area and power limitations. If you can get 4 smaller cores into the area of 1 big core, where the smaller cores are significantly lower power, that's an obvious win for highly multithreaded workloads. By just adding more and more big cores, you're eating die space and likely won't be able to run them all at high clocks anyway due to power/thermal limits.

[Xlucine]

I'd like to see intel cram as many small cores as possible in a server. It'd be a laugh

AdoredTV Jim,leaked an Intel roadmap. It seems Intel is going to be at 8C for the next few generations,but adding lots of Atom cores,to bump up thread count.

It also seems the mainstream is going to be stuck at 6C(big cores) for a few years at least,and might not even get many of the Atom cores either!

6 big cores with a 7700K/8700K bolted on the side in the i5 segment will mean that AMD has to go >6 core to compete

As an aside, I am interested to see if they really are "as good as Skylake" because if so, then Intel does have some interest edging but it begs the question, this is at ISO frequency (which I presume is locked and matched frequencies) so if they can't clock as high but have the same IPC then they may not be able to go as far as Zen 2.

ISO power, not frequency (and even then it's slightly less power than skylake)

[Tabbykatze]

ISO power, not frequency (and even then it's slightly less power than skylake)

It's been many a year since I believed anything Intel has to say in their slides. Out of the big three I find Intel to be the least trustworthy in these aspects, follow by now a joint tie between AMD and Nvidia

[CAT-THE-FIFTH]

This might also explain the TDP increase:
https://videocardz.com/newz/amd-zen4...rated-graphics

Maybe there is a higher end model with 24 cores and an IGP. That would sound pretty awesome TBF!!

[DanceswithUnix]

This might also explain the TDP increase:
https://videocardz.com/newz/amd-zen4...rated-graphics

Maybe there is a higher end model with 24 cores and an IGP. That would sound pretty awesome TBF!!

I wonder if things have gone full circle again here.

There was a time when chipsets became pad limited on the silicon, so there was spare silicon area on the north bridge chip. A GPU was added to make use of that spare silicon in a way that helped sales.

Now the IO controller chiplet (which is pretty much a north bridge in old money terms) is being shrunk to 6nm, but the pads around the outside don't shrink so if AMD were using the whole perimeter then the area inside stays the same. That could be a lot of transistors to use.

[kalniel]

I'd rather have more cache Even L4+ or eDRAM type stuff.

[DanceswithUnix]

I'd rather have more cache Even L4+ or eDRAM type stuff.

ISTR that was the trick with the early NForce chipsets, using spare northbridge space for cache and prefetch buffers (fed by the revolutionary dual channel ram)

[watercooled]

If the GPU were to go onto the IO die, I wonder what implications that would have for reusing that die for the chipset? Assuming they're planning to do the same as X570 of course.

If they really are pad-bound, I guess it's effectively some dark silicon to help with thermals/yields.

[kalniel]

If the GPU were to go onto the IO die, I wonder what implications that would have for reusing that die for the chipset? Assuming they're planning to do the same as X570 of course.

If they really are pad-bound, I guess it's effectively some dark silicon to help with thermals/yields.

Allows them to reuse the chip if the fault is in the GPU area I guess, though it would be neat if they could use DX12 move engines/storage acceleration

[watercooled]

Or.... Crossfire?

[DanceswithUnix]

If the GPU were to go onto the IO die, I wonder what implications that would have for reusing that die for the chipset? Assuming they're planning to do the same as X570 of course.

If they really are pad-bound, I guess it's effectively some dark silicon to help with thermals/yields.

The GPU needs to be near the memory controllers, and that's the IO die. It just all seems to tie in.

If it is otherwise dead space, they don't lose anything by not using it in a chipset variant.

Or.... Crossfire?

I'm just wondering if they would add some sideport HBM3