HEXUS mistake w/ AMD's Quad-Core cache.

[Super XP]

Hi, I like Hexus articles & reviews; I am always on your site reading. I thought I bring this to your attention because many forums including Hardware Analysis do not find you guys at all credible anymore.

And this is the reason. In two articles/reviews posted by HEXUS they say that the AMD Athlon 64 X2 & Quad-Core both share the L1 & L2 cache among all the cores. Now my understanding is that the L1 & L2 cache are exclusive & independent per core where as the new L3 cache is the only cache which is shared.

According to AMD, they do not have a shared L2 cache. That would be pointless and detrimental to performance. Intel on the other hand has an inclusive L1 & L2 cache. There L2 cache is shared from my understanding.

But anyway, I thought I bring this to your attention, because it started a ruckus in several forums including HWA being on top of the list.

[kalniel]

And this is the reason. In two articles/reviews posted by HEXUS they say that the AMD Athlon 64 X2 & Quad-Core both share the L1 & L2 cache among all the cores. Now my understanding is that the L1 & L2 cache are exclusive & independent per core where as the new L3 cache is the only cache which is shared.

This is correct - but I missed where Hexus have said otherwise

[Super XP]

This is correct - but I missed where Hexus have said otherwise

Sorry, I needed to have at least 5 posts in order to post the link.

So, here you all go.

Quote from HEXUS:
The shared Level 3 cache will further reduce wasted clock cycles and keep the cores running at full pelt, plus all four cores can already access each-other’s Level 2 at core speed, as with the Athlon 64 X2.

LINK:
http://www.hexus.net/content/item.php?item=7004

And just for reference, your site is not the only one posting stuff like this.

Quote from the Hardocp:
So, now we have 2MB L2 cache along with the 2MB of L3 cache. Not to mention the L1's also. They are all shared across the board.

LINK:
http://enthusiast.hardocp.com/articl...ZW50aHVzaWFzdA

Take Care,

[Agent]

Each core has its own individual Level 2 cache AFAIK.
Performance could be pretty bad if it was entirely shared. Cores could end up fighting for the same cache in high processing situations, leading to worse performance.

The only thing I can think of is the word “access” being used. Perhaps the cores can read each others cache, but not write to them?

I dont work for HEXUS. Im just a mod

[James Morris]

AMD64 processors have been able to share L2 cache since launch. First, with dual-processor setups it was via HyperTransport. Then, with dual-core this was performed via the System Request Queue at core speed. It's part of the Direct Connect architecture. With a multi-core or multi-processor AMD64 setup, if the required data isn't in the core's local L2, it first asks the other cores if it's in theirs. Only then will it make a memory call, either via its own memory controller or via another processor's. AFAIK, this doesn't include L1, but I may be wrong on that as AMD's L1/L2 has been complicated since the K6!! But I'm confident that the L2 is shared between all cores. It's not one big pool of L2 - each core has its own - but they can all access the L2 on each-other, in a caring sharing arrangement.

[Zak33]

in a caring sharing arrangement.

we love you

[James Morris]

we love you

I must say, that makes me feel both warm and cuddly inside.

[Super XP]

AMD64 processors have been able to share L2 cache since launch. First, with dual-processor setups it was via HyperTransport. Then, with dual-core this was performed via the System Request Queue at core speed. It's part of the Direct Connect architecture. With a multi-core or multi-processor AMD64 setup, if the required data isn't in the core's local L2, it first asks the other cores if it's in theirs. Only then will it make a memory call, either via its own memory controller or via another processor's. AFAIK, this doesn't include L1, but I may be wrong on that as AMD's L1/L2 has been complicated since the K6!! But I'm confident that the L2 is shared between all cores. It's not one big pool of L2 - each core has its own - but they can all access the L2 on each-other, in a caring sharing arrangement.

From what I've read about AMD's Athlon 64's, is there L1 & L2 cache is completely dedicated to there individual core. So, no they do not share the L2cache at all. This is what AMD's A64's are famous about.

If they did have a shared L2 cache, there would be a lot of problems with that sort of design.

Intel's Dual Core's on the other hand do share the L2 cache. Also, to point out, Intel uses "Inclusive" cache design which means that the L1 is within the L2 cache, so in other words, if the L1 stores something, it is also storing in the L2 & taking up space.

AMD's Cache design is called "Exclusive" cache design which means the L1 is & L2 are completely independant of each other, which in turn produces better performance IMO.

[kalniel]

There's a difference between having independant caches but being able to access the other cores cache, and having a pooled cache.

Core 2 Duo has a single, pooled cache. That means that each core can access the entire L2 cache without performance hit.

AMD dual core has independant caches, which each core can access quickly, however they also have to be able to communicate between cores, and this is done via the crossbar isn't it? This is slower than having direct access to the cache, but still (theoretically) faster than having to go out over either hypertransport or (horror of horrors) over the FSB as per pentium D.

[James Morris]

Thanks, kalniel. I'm afraid you are wrong, Super XP. The difference between 100 and 200 series Opterons (and why the former can't be used in multi-processor setups and the latter can) is that the 200s have coherent hypertransport links. This means they can be used to share cache coherency information, which regular HT links can't be used for. This is how they share information between L2 caches. As kalniel says, this isn't as fast as one pooled cache, but it's faster than having to make a call to main memory.

On a dual-core processor HT isn't used. Instead, the System Request Queue and Crossbar communicated the cache coherency information. But the principle is otherwise the same.

However, you are right about the inclusive and exclusive L1/L2 cache - this has been an AMD advantage since the K6-III.

[Super XP]

Thanks, kalniel. I'm afraid you are wrong, Super XP. The difference between 100 and 200 series Opterons (and why the former can't be used in multi-processor setups and the latter can) is that the 200s have coherent hypertransport links. This means they can be used to share cache coherency information, which regular HT links can't be used for. This is how they share information between L2 caches. As kalniel says, this isn't as fast as one pooled cache, but it's faster than having to make a call to main memory.

On a dual-core processor HT isn't used. Instead, the System Request Queue and Crossbar communicated the cache coherency information. But the principle is otherwise the same.

However, you are right about the inclusive and exclusive L1/L2 cache - this has been an AMD advantage since the K6-III.

Post a link in regards to AMD's Opterons sharing the L2 cache. From what I've been reading, and what I was told, there L2 cache is completely independant per core, just like the L1 cache.

[James Morris]

Well, I've been told this numerous times by employees of AMD - technically savvy people like Dave Everett. But here's a quote from The Tech Report which echoes what I've been told:

AMD sought to address this problem by making use of a cache coherency protocol called MOESI, which adds a fifth possible state to its quiver: Owner. (MOESI is used by all Opterons and was even used by the Athlon MP and 760MP chipset back in the day.) A CPU that "owns" certain data has that data in its cache, has modified it, and yet makes it available to other CPUs. Data flagged as Owner in an Opteron cache can be delivered directly from the cache of CPU 0 into the cache of CPU 1 via a CPU-to-CPU HyperTransport link, without having to be written to main memory.

You can find the rest of the article here:

http://www.techreport.com/reviews/20...5/index.x?pg=2

So I'm really not alone in my understanding. It's pretty much common knowledge.

[FatalSaviour]

From what I've read in the past, and from my own understanding, Mr Morris is correct in this SuperXP, sorry.

To confirm, each core has it's own independant cache, but can access the other's, as James explained above.

[Super XP]

From what I've read in the past, and from my own understanding, Mr Morris is correct in this SuperXP, sorry.

To confirm, each core has it's own independant cache, but can access the other's, as James explained above.

Wrong, and Mr. Morris is also wrong. The only cache which AMD CPU's share is there L3 cache for the upcoming Quad-Cores.

All other Dual Core's have independant L1 & L2 cache, NOT Shared. You can read all about it on AMD's Web Site

This FACT alone is what makes AMD's CPU's different from Intel's past & present CPU's.

Quote:
AMD's dual-core microprocessor design sports two CPUs, or cores, each with its own L2 cache.
http://www.devx.com/amd/Article/26686

Quote:
Each of the K8 cores has its own, independent L2 cache onboard, but the two cores share a common system request queue.
http://www.techreport.com/reviews/20...5/index.x?pg=2

Anyway this is just common FACT.

[James Morris]

O...kay....

You just referenced the same Tech Report article where, further down from your quote, it expressly states that MOESI allows one core to access the contents of the other core's L2 cache over the system request queue. And the previous article didn't seem to contain any evidence to the contrary. Sure, each core has its own L2 cache, but it can get data from the other core's L2 cache, exactly as I have been arguing throughout this thread.

Please don't take any of this personally. I'm not trying to make you look stupid here. But I've had this explained to me directly by AMD technical people, so I really do understand how this works and you are not correct on this occasion.

[Super XP]

O...kay....

You just referenced the same Tech Report article where, further down from your quote, it expressly states that MOESI allows one core to access the contents of the other core's L2 cache over the system request queue. And the previous article didn't seem to contain any evidence to the contrary. Sure, each core has its own L2 cache, but it can get data from the other core's L2 cache, exactly as I have been arguing throughout this thread.

Please don't take any of this personally. I'm not trying to make you look stupid here. But I've had this explained to me directly by AMD technical people, so I really do understand how this works and you are not correct on this occasion.

I've asked several people in other forums which also state that because AMD's L1 & L2 cache are exclusive, they do not in any way share the L1 nor the L2 cache.

Intel CPU's having inclusive cache do indead share. Show me proof on AMD's technical Dual Core info & then I may believe. But right now, I told people in other forums what you said, and they think I do not know what I am talking about ???

Take Care,