HEXUS mistake w/ AMD's Quad-Core cache.

[manwithnoname]

O.K. thanks for the definitions. That is exactly what I’ve read & thought.

My point is that the Athlon 64 X2’s do not share L1 nor L2 cache period. If you look at the basic Athlon 64 X2 architectural design, both CPU’s on the single die only share a 144-bit (72-bit x 2) Integrated Memory Controller.

Each CPU communicates with each other via HTT link running at the CPU core Frequency. The Integrated Memory Controller also runs at the CPU core Frequency.

The L1 & L2 cache are in no way in communication with the other processor.
Just look at this AMD link. This should explain all, and look at the design too.

http://www.amd.com/us-en/Processors/...E13043,00.html

Take Care,

You can never find a decent diagram when you need one, have a look at page 15 on this http://www.amd.com/us-en/assets/cont...docs/40555.pdf
(the document is all about accessing memory on different sockets of a multi socket system):

Both cores <-> linked to the System Request Interface (SRI) <-> linked to the Crossbar (XBar) <-> linked to the memory controller (MCT) and HyperTransport link(s). I'm sure that even this is a bit simplistic as well. (AMD just put enough info into the diagrams to help explain the document that contains it.)

Consider core0 reads address A0 - it gets the data from main memory and puts it in its cache, then core1 reads address A0, lets say core0 does not give the data to another other cores (one of those loner cores that keeps themselves to themselves) A0 is read from main memory and puts it in its core1 cache. Core0 updates it's cache entry for address A0 with '10' ... core1 updates it's cache entry for address A0 with '30', both then try to update the main memory what should A0 be 10 or 30. Don't answer that! Just explains why you have lots of books and documents on Cache Coherency Theory. BTW it not just a cache problem consider a DMA controller updating A0 after the cores have read the address.

In AM2 X2s, each core has access to 128 KB L1 Data, 128 KB L1 Instructions, and 512 KB or 1 MB L2. They have no access to any other core's caches. It has no way of knowing what the data is in the L2. As far as I know, it's impossible to share an L1 cache because the communication just to reach it would cause the core to wait at least one extra cycle. As far as I know, each core doesn't share anything with other cores besides the die.

Caches need updating so they all agree at any single point time what the data in A0 is, so they will communication with each other. I agree they do not have to supply data to each other but if you read about Cache Coherency Methods you will see that there are opportunities for cores/CPUs to do this.

At a very simple level core0 has read A0, when core1 reads A0 core0 is 'snooping'* the bus sees the read of A0 and invalidates its cache entry. It's a poor implementation (and probably has never been implementation - it's a theoretical solution that creates other problems) there are more complicated, and useful, methods see the web. AMD uses MOESI I cannot see a document on AMD site, google found this: http://www.techreport.com/reviews/20...5/index.x?pg=2)

Funny you should say that...

Interested to see what you can find out, can AMD explain the xbitlabs article?

* sometimes referred to as sniffing

[James Morris]

Today I talked to Patrick Patla, AMD's Director - Server Workstation Division and John Fruehe, Worldwide Channel Market Development for the same division. I asked them about whether the two cores in an AMD dual-core processor can share information in their Level 2 cache with each other over the System Request Queue, and they both emphatically said they could. For me the matter is settled, no matter what tests Xbit labs thinks it has run. AMD dual-core processors can share information from the L2 cache on one core to the L2 cache on another.

[Super XP]

Today I talked to Patrick Patla, AMD's Director - Server Workstation Division and John Fruehe, Worldwide Channel Market Development for the same division. I asked them about whether the two cores in an AMD dual-core processor can share information in their Level 2 cache with each other over the System Request Queue, and they both emphatically said they could. For me the matter is settled, no matter what tests Xbit labs thinks it has run. AMD dual-core processors can share information from the L2 cache on one core to the L2 cache on another.

I say they do not share L1 or L2 cache. From what you are telling me, AMD says that they can, but "They Can" & They Do" is a different story. And as far as I am concerned they at this point do not share L2 cache. The same goes for there upcoming Quad-Core. L3 is a different story.

[ikonia]

Super_XP,

I've been reading through some of your other posts and you are a very keen AMD pro-active supporter. Which is great.

My questions / comments with regarding this thread.

1.) Super_XP are you honestly trying to debate this or are you just trying to say "AMD is better"
2.) Where are you getting your information from, I'm not saying its wrong, but I've only seen quotes from other forums (a dead source) and the AMD website which both yourself and James Morris agree has conflicting information.
3.) The information James is providing is direct from the AMD technical department, and therefore holds slightly more water as its "hands on" rather than marketing, thats not to say its wrong, just a lot less doubtful.
4.) Super_XP your not putting your point across very well - your coming across as (I hate this term) an AMD Fan Boy, again this is further backed up by the way you argue with a person who actually works for intel on the intel chips capabilities in other threads. Again thats not to say its wrong to debate, most of this thread (bar the approach of your posts) is very interesting.

I'd certainly appriciate a definitive answer, as I find it weak that AMD's hands on information differs from their marketing information.

James is there a chance you could get a definitive answer without leaving certain phrases open to debate eg: "can use shared cache" - to "does/does not use shared cache" then we can put this debate to rest.

[manwithnoname]

I say they do not share L1 or L2 cache. From what you are telling me, AMD says that they can, but "They Can" & They Do" is a different story. And as far as I am concerned they at this point do not share L2 cache. The same goes for there upcoming Quad-Core. L3 is a different story.

Something that suggests "They Can and They Do" is the multi core /multi socket Opteron servers. The makers of those systems would have picked up on this then were building, testing and validating the systems. If someone could prove it didn't work you would expect, quite rightly, that the intel PR team to be advertising the fact: AMD chips faulty, MOESI cache design is not implemented correctly.

James your post is ambiguous. Did AMD give you the ambiguous response or did you post that without realising it?

[James Morris]

I can't believe we're still debating this. AMD told me that its dual-core processors can and do share their L2 cache over the System Request Queue. It's not one big shared cache like with Intel's SmartCache, but one core can request data from another core's cache. I've been told this by so many AMD employees now it's either a big companywide cover-up or maybe, just maybe it's actually true...

[chuckskull]

I can't believe we're still debating this.

^

[largon]

I asked them about whether the two cores in an AMD dual-core processor can share information in their Level 2 cache with each other over the System Request Queue, and they both emphatically said they could.

This doesn't really help us at all as cache coherency traffic goes through the SRQ no matter what route it is performed, be it cache-to-RAM-to-cache or cache-to-cpu_core_logic_x-to-cache.

In post #19 the quoted text from AMD's datasheet unambiguously says "MCT [memory controller] maintains cache coherency and interfaces with the DRAM". Thus cc traffic definately goes all the way to the MC, the million dollar question is whether the MC merely passes the data to RAM or does it talk to both of the L2s directly.

[Clunk]

Christ on a bike

[Splash]

Am I the only one bored of this thread?

[largon]

Spamming seems to be a popular pastime on this forum...

[Stoo]

I think this is best of being closed as it's going nowhere and it's starting to collect spam..