AMD - Piledriver chitchat

[scaryjim]

According to Semiaccurate, these new parts are actually new dies ....

The embedded parts are, and according to those articles they were created for the embedded market due to the target power and (in the case of the LX chips in particular) cost. If those are also moved into the consumer market, I think it'll make it the first time a die has been designed for the embedded market then transitioned into the consumer market - previous releases (certainly in the last 5 - 10 years) always seemed to come to the consumer market first then get pushed into the embedded...

[watercooled]

Oh I misread your original post, I'll blame AMD's interesting naming system but I thought you meant a harvest of an existing die. But yeah, it does seem like something in-between the two embedded parts.

It does look like it gives Core M a run for its money under some workloads though, and I wonder how it compares in terms of efficiency? TDP probably isn't a reliable indicator as Core M's 'TDP' really isn't indicative of load power.

[CAT-THE-FIFTH]

The first test of the X4 845:

http://www.jagatoc.com/2016/03/hands...rah-tanpa-igp/

The power consumption savings are massive over the X4 860.

[watercooled]

Excavator really is quite impressive from what I've seen of it - makes me wonder why they didn't bother with a proper desktop release of it rather than a barely-mentioned mobile update.

I'm definitely interested in an Excavator-based APU for my quiet PC, it's currently on Llano and I do find myself wishing wanting a bit more single-thread performance at times, but with enough GPU grunt to cope with a few less demanding games.

[CAT-THE-FIFTH]

An extensive user review of the X4 845:

http://excavator.looncraz.net/

Considering the lack of L2 cache it is still reasonably faster than a similar clockspeed Kaveri CPU in almost all benchmarks,and seems to hit 3.8GHZ consistently unlike the A8 7600 which cannot. However,it does seem the lack of L2 cache does stifle the performance increase,since it affects MT scores - some of the ST improvements look quite decent IMHO.

Still quite a way to get to SB levels of IPC but again the 2MB of L2 cache is affecting performance. Would be interesting to see if Bristol Ridge has 4MB of L2 cache.

[CAT-THE-FIFTH]

It seems Zen launches in October with an 8C/16T chip is supposed to be between Broadwell and Haswell IPC:

http://wccftech.com/amd-zen-cpu-8-co...ching-october/

Not sure if I can believe the IPC claim though!! It would be awesome if true!!

[DanceswithUnix]

Not sure if I can believe the IPC claim though!! It would be awesome if true!!

If true and they can get close to 4GHz out of it

[CAT-THE-FIFTH]

Saw this on SA forums(after it was mentioned on AT forums) but OFC take with bucketloads of salt:

https://semiaccurate.com/forums/show...postcount=2112

It seems that unlike with Bulldozer, AMD has created separate dies for server and consumer parts. The server version of the die has twice the cores, L3 cache and additional I/O controllers per die. I haven´t been able to disassemble one yet, however judging from the package size it is a MCM part. 14nm LPP process.

The relative power consumption is roughly the same as on Intel 14nm parts with similar configuration, but the clocks are quite low :/

40501415

For a long time I actually like what I see. I´d say as long as the consumer Zen parts can reach high enough clocks (min. 3.5GHz), everything will be pretty good

Apparently the poster who made the posts had some information on Carrizo which was correct according to that thread.

[watercooled]

If I'm reading it correctly, he claims separate dies based on doubling of cores, cache, IO, but then goes on to mention MCM? Unless he means the individual dies carry those properties, MCM means multiple dies per package, which does not contradict using the same die?

[CAT-THE-FIFTH]

If I'm reading it correctly, he claims separate dies based on doubling of cores, cache, IO, but then goes on to mention MCM? Unless he means the individual dies carry those properties, MCM means multiple dies per package, which does not contradict using the same die?

Unless the chip he looked at had a MCM of two server dies,and the consumer die is smaller??

I wonder if AMD is going to just have 4 cores and 8 threads for the consumer version,but try to maximise clockspeed,plus have quite a small chip for the consumer parts??

If they lack an IGP that could make the parts relatively cheap to make,and maximise yields??

The current Core i7 6700K sells for nearly £300 and has a 122mm2 die IIRC and half that is the IGP too!

Makes me wonder if AMD is trying to make sure lower profit margin consumer parts don't have massive dies??

[watercooled]

They could end up being pad limited with something as small as a 14nm quad core CPU with no IGP though. It's quite possible be meant 16C+16C MCM, especially if they've had interest from the likes of CERN - the development cost probably wouldn't be much on top of a 16C die itself.

[CAT-THE-FIFTH]

Apparently on AT forums another poster has stated another chap,who IIRC has a decent record on things,said Zen was about Broadwell levels of effiency.

If AMD can get to Broadwell levels of effiency and Haswell/Broadwell levels of IPC,that would be a big deal especially if they can get reasonable clockspeeds.

[Xlucine]

I'm still convinced that a big interposer could help with pad limited CPU's, since the bumps for a silicon to silicon connection can be packed smaller. QC on the interposer would be easy as well, you only need continuity from the pins on one side to the pins on the other side

[watercooled]

That's an interesting point, however I wonder how cost would factor into it as they would possibly be most useful with the smaller/lower cost dies?

[DanceswithUnix]

I'm still convinced that a big interposer could help with pad limited CPU's, since the bumps for a silicon to silicon connection can be packed smaller. QC on the interposer would be easy as well, you only need continuity from the pins on one side to the pins on the other side

I believe the savings from interposers come from the reduced current drive needed to talk to another die on the same interposer. As soon as you are going off package, you need a big driver pad on the silicon to talk off chip so the size of the connection bump isn't really an issue. So, interposers only make sense if you have more than one die on there.

Not heard people complain of being pad limited for years now, I think they are just better at making rectangular rather than square chips.

[scaryjim]

... As soon as you are going off package, you need a big driver pad on the silicon to talk off chip ...

I believe part of the pad size issue is that silicon and package substrates expand at different rates when heated, so you need a larger pad to maintain the connections when the chip heats up. Using an interposer removes the thermal stress issues so you can use micro-bumps on the actual chips. However, I doubt that making a smaller chip AND an interposer would be significantly cheaper than making a slightly larger with slightly larger bumps/pads - after all, if you're pad-limited on the smallest chip you can make you can just cram more transistors into it...