What function does this circuit perform

[cameronlite]

Hi guys,

I'm looking over a past paper in prep for my exam next week and it asks me to derive the logic function of the circuit below.

Any ideas guys? If you do, could you please explain WHY it is what you say it is please

Cheers.

[Gerrard]

OK, it's been a few years since I've done this (when I studied at Soton Uni coincidentally!)

Y = E + F + G + H
E = A.C
F = B.C.D
G = A.C.D
H = A.B

Can't see anything obvious in that form, so making a truth table can help: -

A | B | C | D | Y
------------------
0   0   0   0 | 0
0   0   0   1 | 0
0   0   1   0 | 0
0   0   1   1 | 0
0   1   0   0 | 0
0   1   0   1 | 0
0   1   1   0 | 0
0   1   1   1 | 1
1   0   0   0 | 1
1   0   0   1 | 1
1   0   1   0 | 1
1   0   1   1 | 0
1   1   0   0 | 1
1   1   0   1 | 1
1   1   1   0 | 1
1   1   1   1 | 1

To be honest, still can't see anything of particular interest in there other than 2 lots of 4, but I'll leave my working to a) be checked and b) if someone else notices something. Unless it's just after: -

Y = A.C + B.C.D + A.C.D + A.B

[cameronlite]

Thanks for your reply. Here's the question - incase I have misinterpretted it.

[Whiternoise]

Can you minimise the logic further? The question seems to suggest that one of the inputs is redundant, but I have no idea what a path sensitive algorithm is in this case.

I'd suggest take a look at the Karnaugh map?

[cameronlite]

Can you minimise the logic further? The question seems to suggest that one of the inputs is redundant, but I have no idea what a path sensitive algorithm is in this case.

I'd suggest take a look at the Karnaugh map?

The only important part of the question is the first sentence - for now

Minimising the logic won't minimise the truth table though, so it will still perform the same, surely?

[Gerrard]

Right, think it's on about race hazards due to the addition of NOT gates. You can use a Karnaugh map to make them more obvious: -

  AB | 00 | 01 | 11 | 10
CD   |    |    |    |    |
--------------------------
00   |    |    |  1 |  1 |
--------------------------
01   |    |    |  1 |  1 |
--------------------------
11   |    |  1 |  1 |    |
--------------------------
10   |    |    |  1 |  1 |

I think in this case, race hazard can occur when A=1, B=0 and D=0, and C changes. This is because you can move between two adjacent 1s without it being grouped, ie the green to the blue (quite difficult to demostrate without drawing). You can fix this by adding another group: A.D

As for path sensitive analysis, I think that is to do with one of the signals changing, but the delays on the gates means you get a "spike" on the output due to one of the inputs to the gate being delayed by the NOT gate compared to the others, ie a race hazard. So I imagine if you did a graph of C changing with the above conditions and worked out the output of each gate in time steps, it will spike (either up or down).

NB It has been many years since I've done this stuff, so could just be talking nonsense!

EDIT: It's when C goes from 1 -> 0, because G will switch off before E goes to 1, due to the delay on the NOT gate from C, meaning the output will briefly drop to 0. Still not sure about the stuck condition though.

[Zak33]

/ and this is why Zak didn't study this subject, cos frankly not only does it make me tense.. it makes me angry

and I just don't know why either.

[cameronlite]

Thanks for the info Gerrard, however, I still don't know what the circuit does...

[Splash]

Thanks for the info Gerrard, however, I still don't know what the circuit does...

Your homework for you?

[Behemoth]

Looks like a Rooster BoosterPaxo Stuffer to me !

[Stoo]

Thanks for the info Gerrard, however, I still don't know what the circuit does...

Makes Zakky angry and fustrated apparently

It's not going to do anything much by itself - it's just a set of logic gates - based on a combination of inputs at A-D, you get an output or not at Y

What you choose to do with it, is entirely up to you

[Stoo]

btw, if you build it using http://logic.ly/demo/ you can just fiddle with the inputs and visualise what happens

Actually, if you go into the settings, and set the "limit propagation to display rate" option, you can visualise the output drop when A is high and C changes from high to low.

[The_Wheelhouse]

The minimised function (from the k-map):
Y = B.C.D + A.C + A.D

Thus A.B is a redundant extra term (in a logical sense), also looking at the k-map with the function drawn in the only term not to overlap is the B.C.D term, so the A.B term corrects a static 1 hazard.

At least that's what I get from the first part of the problem.

[mycarsavw]

btw, if you build it using http://logic.ly/demo/ you can just fiddle with the inputs and visualise what happens

This ^ + Minecraft = Nerdgasm

[cameronlite]

btw, if you build it using http://logic.ly/demo/ you can just fiddle with the inputs and visualise what happens

Actually, if you go into the settings, and set the "limit propagation to display rate" option, you can visualise the output drop when A is high and C changes from high to low.

Ahh, cool. So without the bridging term there's a static 1 hazard (thanks The_Wheelhouse) but we still don't know what it's purpose is. In previous papers there was a similar example - the circuit was the sum part of a 4 bit adder...

I'm going to ask my lecturer today what the answer is...

[cameronlite]

OK guys,

Turns out many of you were right. The answer to the ambiguous question was:

Derive the logic and mention how the redundent logic can be removed to allow circuit testing.

Thanks again guys.