Read more.AMD creates buzz around Shanghai at SC08, but the company's window of opportunity is small.
Read more.AMD creates buzz around Shanghai at SC08, but the company's window of opportunity is small.
With the FPU. With Santa Rosa, float performance is about half (!) woodcrest, per cycle per core. Well, on paper anyway (obviously in real life it's not that big a gap). Barcelona increased the theoretical float performance from 2 FLOPs/cycle to 3 - but due to design cock-ups, about 20% of that total performance is lost. Xeon has consistently had 4 FLOPs/cycle (as long as they're the right kind of FLOPs, anyway) since Woodcrest landed, with only the same memory bandwidth problems Xeon's always had causing issues. On purely RAM-bound codes, Opteron DOES tend to do better.
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