19W TDP Mobile A10-7300 spotted:
http://www.cpu-world.com//news_2014/...HP_laptop.html
19W TDP Mobile A10-7300 spotted:
http://www.cpu-world.com//news_2014/...HP_laptop.html
What about putting a SATA RAID card into the only slot on the ITX board or one of the slots on a mATX board.
ECC support would be even better for (home) server purposes.
Could be (out of curiosity) the CGN cores used professionally for anything in a file server position? (encryption, compression for allow faster data streams due to lower volume, etc).
Last edited by Bonebreaker777; 05-05-2014 at 12:16 AM.
SATA cards are expensive enough that I think you are better off with an FM2+ motherboard that comes with 8 ports out of the box.
The only port on my current ITX board is used for the second ethernet port. So I could build an AM1 server that would work for me now, but not with any ability to expand in the future.
Supposedly AMD is introducing a new CPU design in 2015 or 2016 which uses SMT:
http://wccftech.com/amds-high-perfor...-architecture/
Or as with Mantle they can turn the situation to they advantage (even if Mantle will be never an industrial standard, just carrying the characteristics in the next DX is a win already).
Wonder what it would take to have a CPU developed in secret, hire an independent team to test it and if its a no-no, scrap it (I realize the financial aspect but how about the rest)?
I was wondering what direction they'd take after the Bulldozer family was complete - they announced those uarch names well in advance but we're nearing the end of that and nothing else has been revealed yet.
About it being Excavator though - AFAIK that's pretty much confirmed to be Bulldozer-based? One of the other options seems more likely IMO, maybe with Carrizo as planned, but the next FX (or whatever replaces that brand) using the new cores, since we've still not seen any official word on an Excavator FX.
By smaller cores do you mean the cat cores? The SMT rumours I've seen around the net all seem to mention 'high performance' cores. I'm not sure how useful SMT would be in a small OoO core? Intel also moved away from SMT for Silvermont.
I wonder if the SMT rumours we saw with Kaveri had anything to do with this, someone getting their leaks confused maybe?
As a few people have pointed out, I wonder if all of this is a result of the company shake-up which happened a while back? http://www.bitsandchips.it/9-hardwar...ta-nel-2016-17
How can AMD return to traditional SMT when the only threading architecture I know of them doing is the one in Bulldozer?
Nit picking aside, this seems odd partly as it is attributed to Jim Keller. That guy is ex DEC, and CMT has a very DEC feel to it. In the same way that the Alpha had two register files to cut the CPU in half and keep clock speeds high I can see CMT having the same sort of effect of shortening paths to keep clocks up. The only thing that backs this up is that the A6 which Jim had a hand in is a really wide architecture and crying out for SMT. But then A6 isn't as fast as Jaguar.
And who is the referenced "critic"? Not hard to find a critic of anything on the Internet.
Now I must admit I hope it isn't true as I think there are plenty of tricks AMD can try yet. SMT is a done deal. IBM got it fairly nailed years ago with fine issue granularity and up to 4 threads, Sun jumped the shark with 16 threads and laughable results.
Don't read anything into Atom, as a simple in order CPU early ones relied on thread switching to get around stalls.
An interview with the AMD CEO:
http://blogs.wsj.com/digits/2014/05/...y-of-pc-chips/
I did keep thinking that myself TBH.
Doesn't Sun's design only actually execute only two threads per core simultaneously, with the rest being used to keep the execution resources filled and hide memory access latency?
I wonder what the cost/effort involved in getting significantly more performance with CMT would be vs using something more well-understood though? Assuming they want to improve single threaded performance, how far can they go before they approach or exceed the die size/core needed for SMT cores? AMD are already close to Intel when it comes to multithreaded performance per die size on the same node, given that one module is similar in size to one Intel core.
That's what I meant about ditching SMT when they moved to OoO.
It's nice to see some confirmation on x86 core work!
In AMD's 2016+ pane are they suggesting that they're going to be actively developing 64 bit arm and new x86 cores, or that they're going to have an architecture where both are used together?
Both together doesn't sound like a feasible idea with the different instruction sets, but I'd love to have computers with optional (low power ~10W) coprocessors that could keep the OS ticking over along with your browser, mail etc. I suppose that would be kind of like how the current Parallella boards work (but I've no idea what instruction set Epiphany uses)
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