Originally Posted by krustylicious
When I heard about chiplets I did wonder if they might license Intel's EMIB technology - cheaper than a full-on interposer but I believe more performant than standard packaging options. And I expect they got at leats a bit of a look at it while they were working with Intel on Kaby G...
Ignoring cost of licensing, EMIB would make the most sense. I'd imagine power consumption and latency could be a bit less than package wiring. Suspect the difference wouldn;t be enough to justify the extra cost and complexity though.
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Why are people obsessed with interposers? They are needed to wire up the thousands of traces to HBM stacks. Threadripper doesn't use one, Epyc doesn't use one, I don't see any reason that chiplets would need one when they use the same fabric interconnect as the existing server parts that just wire stuff together on the organic substrate.
As for EMIB, I can't imagine Intel licensing that to anyone. That just isn't how they roll. Unless perhaps a company used Intel as their foundry, but Intel as a foundry hasn't exactly been a roaring success so far.
Interconnect density, latency and power consumption. Of course with the right chiplet and IO die design, these can be just fine using traces on the substrate.
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which was my point. No HBM memory, no need for interposers. Perhaps if AMD do a really quick APU they will need one if they add HBM.
Interposers aren't just useful for HBM memory. Any situation where you need thousands of traces and can't fit that many on the substrate is a use case for an interposer/EMIB. Only one of which is HBM.
Two examples I can think of from the top of my head: Huge, low power bandwidth between chiplet and I/O die. Maybe it's got a very high bandwidth L3/L4 cache. More traces means either a lower clockspeed for the same bandwidth or even more bandwidth. Second example is chiplet to chiplet comms. With EMIB/an interposer the bandwidth, power consumption and latency between chiplets will not be much worse than if they were on the same die. Using traces on the substrate increases power and/or latency and/or reduces bandwidth.
I'm not saying an interposer/EMIB is the best design BTW. It probably isn't for Ryzen 3 for cost reasons, however there are valid reasons to use it other than HBM.
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That wouldn't be InfinityFabric, which given the context here pretty much rules it out.
I'm also not saying that an interposer is impossible in a ryzen design, I just think people are assuming it is needed when in most cases it wouldn't. If chiplets use IF, like Threadripper does, then it isn't needed.
Who's the person obsessed with interposers you're referring to? I only mentioned it as a comparison point, not a serious suggestion for Zen 2.
Joking aside i get where you're coming from Dances however things really have moved on from what used to typically be called interposers and substrates, in the past interposers (afaik) used to generally be high density passive silicon layers and substrates used to generally be a low density way of fanning out the higher density of connection on a silicon die into something more manageable.
However that's not really the case these days, it's now possible to use organic substrates (2.1D) to connect dies within a MCM.
Advanced Packaging Confusion.
With need to put all of this in a framework,” said Ravi Mahajan, an Intel fellow. “With any new architecture, you need a way to bucket-ize it. And if the framework is defined well enough, you need to achieve consensus across the industry. So if you look at photonics, there’s a fairly decent set of papers. But some of these use a silicon interposer, some use a bridge, and some are using organic interposers, which are catching up to the others. There are differences in the densities. We also see glass interposers coming into the market.”
EDIT: BTW I'm not saying either of us are right or wrong, I'm saying we're both right and wrong as the whole advanced packaging/interposer/substrate thing has been very much up in the air in the last few years.
Last edited by Corky34; 14-12-2018 at 07:13 PM.
My only thought on that was that Threadripper's cross-die latency is pretty poor compared to on-die - if you look at the 2700X & 2990WX (which is defaulted to local memory access) you're looking at 72ns latency, while the 2950X averages out at ~ 95ns. That's difference between the on-die memory access and the cross-substrate memory access. A chiplet-based design is going to depend on off-silicon memory access, so that latency is going to impact performance - so if using an interposer or EMIB would bring that latency down, it might be worth it...
But that is *precisely* my point. If you are making a mainstream CPU, then you need at least 1500 connections and therefore are using an organic substrate to package the chip. The capabilities of that packaging, as shown in things like ThreadRipper, are quite impressive.
Now you could use a standard organic package and an organic interposer for the fancy connections. But as an engineer that is repulsive. Imagine telling someone to make 100 thick sliced sandwiches by slicing the bread really thin and then interposing another thin slice between the outer slice and the filling to make the bread thicker. No, just slice the bread thick to start with, and save yourself a ton of work in the long run.
I would imagine that is down to going through a pair of SerDes units on that path (one off chip then another back on chip at the other side). An interposer would reduce off chip capacitance, but I would have to wonder if it was by enough. If you look at HBM memory speeds, they need huge width to make up for the fact the parallel connections are slow. You go through a SerDes, you don't need so many connections for the resulting serial channel, so you can drive the fewer bumps with more power and hence faster. So yes it might be worth it, and I'm sure someone at AMD has run the simulations: Serial over package vs serial over interposer vs parallel over interposer. The interposer may have a cost in power distribution (it always boggles me to think modern CPUs draw around 150A through those little bumps) as well as a benefit in data connection speed.
One of my first thoughts when the chiplet idea turned up in the news: If ram accesses all happen through the central hub, then you always get a slow down. If each chiplet contained one memory channel then ram bandwidth would scale with chiplets, and each chiplet would have some local ram. Not sure what the state of NUMA support is in Windows, but Linux should cope with that fine for the server market. I'm a little surprised if they are going for what is basically an old northbridge design, but perhaps that is down to 7nm being poor at power intensive memory controller implementation. Interesting times
The things is when you say interposer, that TR & Ryzen don't use them, what spring to my mind is something (organic, silicon, glass, whatever) with wires running through it connecting one IC to another and by that definition they do use interposers, yes we call it a substrate but that's only because it's at the lowest level.
It's just one of those silly things that gives me that nails down a blackboard feeling i guess.
BTW I came across this video on Semiconductor Engineering's YouTube channel that i found interesting in reference to chiplets.
Given the results of the different Threadripper configurations it seems to be pretty good.
I'm really looking forward to seeing what they've come up with. The thing is, I've got so many cool ideas about what they might do that the reality is almost certainly going to be disappointing compared to that!... I'm a little surprised if they are going for what is basically an old northbridge design, but perhaps that is down to 7nm being poor at power intensive memory controller implementation. Interesting times
The other problem is that cool ideas don't always equate to something fast. I thought piledriver was a cool idea, but in reality it didn't perform as well as something less elegant.
Follow-up on the claims that breaking compatibility was necessary for 6 core Skylake: https://www.youtube.com/watch?v=cMY-EEFkGVk
It would seem not. I wonder if Intel will be more inclined to preserve compatibility now they have decent competition in the CPU space again, and having to change motherboards anyway means switching to a competitor isn't as big of a step.
I wonder if it has anything to do with why their 8 core CPUs do preserve compatibility? After all, they demand more power than the 6 cores, like the 6 cores needed more than 4...
It's now confirmed that Ryzen 3000 series/Zen 2 uses a 7nm chiplet and a 14nm I/O die. My first question i whether it's the same I/O die as Rome with bits fused off or a smaller one for just one chiplet. If so, I expect the same one to be used for Threadripper 3 of course.
Maybe they can justify a separate I/O die for Ryzen 3000 series due to die space savings on a hopefully very high volume part.
Exciting times regardless!
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