Little history of CPUs

[Cov]

CPU ........................ Rel............. Frequency ........... Transistors .............. Process............... L2 Cache

8086 ....................... 1978 ........... 5 – 10 MHz .......... 29.000 .................... 3 µm
80286 ..................... 1982 ........... 6 – 25 MHz .......... 134.000 .................. 1.5 µm
80386 ..................... 1985 ........... 20 – 33 MHz ......... 275.000 – 855.000 .. 1 µm
80486 ..................... 1989 ........... 25 – 100 MHz ....... 1.6 Mio ................... 0.8 / 0.6 µm
Pentium 1 ............... 1993 ........... 60 – 233 MHz ....... 4.5 Mio ................... 0.35 µm
Pentium 2 ............... 1997 ........... 233 – 533 MHz ..... 7.5 – 19 Mio ............ 0.25 µm
Pentium 3 ............... 1999 ........... 450 – 1.4 GHz ...... 28.1 Mio ................. 180 / 130 nm
Pentium 4 ............... 2000 ........... 1.4 – 4 GHz ......... 42 – 55 Mio ............. 90 / 65 nm ............ 512 KB
Pentium D ............... 2005 ........... 2.8 GHz .............. 230 Mio .................. 65 nm ................... 2 MB
Core 2 Duo .............. 2006 ........... 1.86 – 3.16 .......... 291 Mio / 410 Mio ... 65 / 45 nm ............ up to 6 MB
Cor 2 Quad .............. 2006 ........... 2.4 – 3.2 GHz ...... 586 / 820 Mio ......... 65 nm / 45 nm ....... up to 12 MB

(Source: Wikipedia)

1 µm = 1000 nm
45 nm = 0.045 µm

Conroe is Inte's E6000 series
Kentsfield is Intel's Q6000 series 2 x Conroe on one die

Wolfdale is Intel's E8000 series
Yorkfield is Intel's Q9000 series 2 x Wolfdale on one die

Nehalem will use the 45 nm process and maybe due end of 2008 / beginning of 2009
Westmere ... (shrinked version of Nehalem) ... will use the 32 nm process and is due from 2009 onwards.
Sandy Bridge ... (new generation) ... comes first in 32 nm and later in 22 nm from 2010 / 11 ... (if Intel stays on target with its roadmap)

[matty-hodgson]

i remember my old P1 in my Windows 3.1 machine!
still got that in the loft/attic..
what a beast that is!
might install Vista on it next week if i find the time!! that's if i can transfer Vista from DVD onto floppy..

Q6600 ftw now though!

[Cistron]

Hmm, if you take the performance of a 8086 10MHz per 29000 transistors and extrapolate how much power half a dual core should have, we should be somewhere around 7GHz. I'm sure the performance of one core 2 duo is better than 1400 8086 though

edit: actually had a fault in my calculations - should be 70 GHz. Back to the roots, lets build 14000 8086 chips onto one Core 2 Duo at 45nm, hehe.

[matty-hodgson]

but remember.. processors have started getting huge L2s and stuff now, which take up massive amounts of transistors, it's not all processing transistors.

[switchmode]

Also some of the transistors are microcode to run the cpu a bit like the cpu firmware but not flash upgradeable !

[rob4001]

My first PC after the fantastic amiga 500 was a 486 dx2/66 bring back the amiga what a machine!

[Cov]

Pentium 1 = 50 mm x 50 mm ... socket 7 / 321 contacs
Pentium 4 = 35 mm x 35 mm ... socket 478 / 478 contacts




I wonder what size the Dual and Quad core CPUs have ? ... LGA 775 / 775 contacts

[DDY]

I still have my 100MHz Pentium MMX somewhere, it's probably installed on a Socket 7 motherboard with some 8MB SIMMs too!

[[GSV]Trig]

My first PC after the fantastic amiga 500 was a 486 dx2/66 bring back the amiga what a machine!

My Dad was on a P120 when I was on my Amiga 1200/1230, oh how I laughed

[j.o.s.h.1408]

i remember my old P1 in my Windows 3.1 machine!
still got that in the loft/attic..
what a beast that is!
might install Vista on it next week if i find the time!! that's if i can transfer Vista from DVD onto floppy..

Q6600 ftw now though!

if u can install vista on that machine i could easily install in on my N95

[TheAnimus]

Hmm, if you take the performance of a 8086 10MHz per 29000 transistors and extrapolate how much power half a dual core should have, we should be somewhere around 7GHz. I'm sure the performance of one core 2 duo is better than 1400 8086 though

The biggest leap in transister useage is all the extra instructions, and support for Rings, and increased bus width.

if you want pure performance per cycle, look at an ARM design.

[kalniel]

The biggest leap in transister useage is all the extra instructions, and support for Rings, and increased bus width.

How many extra instructions does core 2 have? SSE through to SSE4 can't be all that many.

I'd have thought biggest increase was down to the cache.