AMD - Bulldozer Chitchat

[Golden Dragoon]

That always used to be their way, but are they using the llano socket in any servers yet? The server/desktop line seems to be splitting away from each other.

It's less to do with the socket than the silicon, if they release a chip with a hybrid DDR3/4 memory controller, then it is possible that you could get DDR4 supporting servers and DDR3 supporting desktops on AM3++, but unlike DDR2/3 DDR4 isn't a simple "speed bump"* with those the controller was similar enough that it really didn't take much die space to support both, going to 4 would mean having to duplicate an awful lot of the mem controller on the die to support two different standards.

[DanceswithUnix]

But my point was that the server silicon is the same as AM3+ silicon, whereas AMD seem to be pushing FM1 as their main desktop solution.

So, if AMD decide that desktop requires DDR4 then it becomes FM2/3 and servers are not involved (but laptops are).

I expect the dual mode DDR2/3 memory controller is a blip of those technologies being closely related which we may not see again for a while.

[watercooled]

The FM sockets are the ones that would probably benefit most from faster RAM, because of the IGP - even with the 1st gen, Llano, you can see a significant difference between different memory speeds.

[Terbinator]

The FM sockets are the ones that would probably benefit most from faster RAM, because of the IGP - even with the 1st gen, Llano, you can see a significant difference between different memory speeds.

Sort of a downside as well though, as faster RAM naturally costs more.

[watercooled]

There's not much in it between 1333 and 1600 now, but it will be true of any powerful IGP really, considering how much bandwidth discrete cards have.

[Terbinator]

There's not much in it between 1333 and 1600 now, but it will be true of any powerful IGP really, considering how much bandwidth discrete cards have.

Aye, i was thinking more of the 1866+ stuff - although from a technical view it definitely is interesting.

Am i to interpret DDR4 as QPI/HTT rather than FSB, connection wise? Will this also yield better performance when at the same speed as DDR3 given the nature of the connection?

[Biscuit]

for desktop use probably not because the access time will barely change, the difference will be in servers where there is multiple concurrent accesses, as the overall bandwidth allowance will be higher.

[watercooled]

At the same speed, a single module will probably perform similarly, like with DDR2-3, but the lowest speed available will probably be above 2000 MT/s, like top-end DDR3. It should also allow greater capacities relatively cheaply. And yeah like I say it's point-to-point so you'll theoretically get a boost in performance for every bank you fill, which should mostly do away with the current problem of using multiple modules per channel increasing latency. So, like with PCIe, you'll probably get a number of 'lanes' on the IMC.

[CAT-THE-FIFTH]

A Geekbench score for a mobile Trinity A10:

http://semiaccurate.com/forums/showp...postcount=1834

The score is better than a mobile Core i5 dual core running at the same base clockspeed.

[CAT-THE-FIFTH]

Trinity A10-4600M clockspeeds:

http://www.sibvez.ru/shop/UID_13494.html

It seems with laptops already advertising Trinity CPUs already being released,Trinity should soon be out.

The A10-4600M has a 35W TDP AFAIK.

2.3GHz - 3.2GHz

Way to go AMD - lets hope the IPC improvements over BD are sufficient to make up for that lowish base 2.3GHz...

It seems the base clockspeed has now increased to 2.5GHZ and maximum boost clockspeed has decreased to 3.1GHZ:

http://item.gmarket.co.kr/detailview...earch_keyword=

The IGP runs at 685MHZ too.

Supposedly,the HD7670M is VLIW4 based and I wonder if the HD7000 series cards under the HD7750 will be actually new VLIW4 derived ones and not rebrands.

Edit!!

It seems the HD7670M is based on the HD6670 and hence is VLIW5 based:

http://www.kaskus.us/showthread.php?p=678078791

[CAT-THE-FIFTH]

It seems that hardware divider function was blocked in Bulldozer and Llano,but is now enabled in Piledriver and integer performance in tests is significantly higher:

http://translate.google.com/translat...d%3D1334532731

[Terbinator]

Hardware divider function -what is this in laymans?

[watercooled]

Basically it allows the CPU to perform integer divide operations in less cycles than they'd otherwise take.

[DanceswithUnix]

Hardware divider function -what is this in laymans?

Modern AMD and Intel CPUs don't actually execute x86 instructions internally, they translate them into a simpler internal instruction set (sometimes called micro-ops).
Before it would have been generating a little program to do the division, now it just sends the problem to a lump of dedicated hardware.

[DanceswithUnix]

It seems that hardware divider function was blocked in Bulldozer and Llano,but is now enabled in Piledriver and integer performance in tests is significantly higher:

http://translate.google.com/translat...d%3D1334532731

I am rather horrified that there is a benchmark out there that is 25% divide instructions.
Really, no code ever does that (if only because most problems can be converted into faster multiplies).
Some benchmark writers should be shot.

[CAT-THE-FIFTH]

If you look back at the BOINC results I posted earlier,it seems at the same clockspeeds the single thread FP performance is similar to an FX8150,and integer performance is around 10% better for an A10-5800K:

http://citavia.blog.de/

Considering,it has no L3 cache,this is not too bad,and single thread FP and integer performance is much better than an A8-3870K. Considering the TDP is the same,this is a decent improvement in performance/watt. Compared to the FX4100,the CPU section of the A10-5800K should be better and probably will consume less power IMHO.