AMD - Piledriver chitchat

[scaryjim]

The MCM approach they use in current server parts just wires two cores together using an HT link, so if they lose HT they can't do that. I don't think PCIe is really suitable for NUMA inter CPU connection.

Perhaps they could include an HT link in the FM2+ silicon, and just leave it disabled on the consumer part. Die photos show unused PCIe lanes on the 8350, so unused port pins doesn't seem to do any harm.

Not sure why PCIe wouldn't be suitable for interCPU connects? I guess it might be a bandwidth limitation still, although PCIe 3 x8 is pretty close to the bidi bandwidth of 16bit HT, and PCie 4 x8 will surpass it. Otherwise surely it just needs a bus to communicate down, and the nature of that bus is kind of irrelevant?

That said, I'm pretty sure that FX silicon already has 4 HT links implemented and for the AM3+ package three of them are simply ignored, so undoubtedly if that's the way AMD wanted to go they could just continue to put unused HT links on the silicon and only enabled them for the opteron chips. I guess that would come down to whether it's a good use of silicon space though...

[CAT-THE-FIFTH]

This is the thing,we might be thinking of Mantle the wrong way. It seems AMD is probably using it more to extend the life of their CPUs for gaming.

[DanceswithUnix]

Not sure why PCIe wouldn't be suitable for interCPU connects? I guess it might be a bandwidth limitation still, although PCIe 3 x8 is pretty close to the bidi bandwidth of 16bit HT, and PCie 4 x8 will surpass it. Otherwise surely it just needs a bus to communicate down, and the nature of that bus is kind of irrelevant?

That said, I'm pretty sure that FX silicon already has 4 HT links implemented and for the AM3+ package three of them are simply ignored, so undoubtedly if that's the way AMD wanted to go they could just continue to put unused HT links on the silicon and only enabled them for the opteron chips. I guess that would come down to whether it's a good use of silicon space though...

For inter-CPU you want low latency and good cache snooping. PCIe is more about bandwidth, using large posted write buffers. Read-modify-write accesses across PCIe tend to be rather sucky.

Thinking about it, just two HT links should get you an OK quad socket, or 2 die MCM with dual socket. That would probably be enough these days, I can't see that many 8 socket machines getting sold.

[DanceswithUnix]

This is the thing,we might be thinking of Mantle the wrong way. It seems AMD is probably using it more to extend the life of their CPUs for gaming.

If they pull it off there are only up sides for them.

Top end graphics card still a bottleneck with your existing CPU? Best go crossfire then

Might make FM2+ a socket of choice for gaming as well if it is all about GPU, as PCIe3 will become an issue.

[scaryjim]

For inter-CPU you want low latency and good cache snooping. PCIe is more about bandwidth, using large posted write buffers. Read-modify-write accesses across PCIe tend to be rather sucky.

Fair enough, that makes some sense.

Thinking about it, just two HT links should get you an OK quad socket, or 2 die MCM with dual socket. That would probably be enough these days, I can't see that many 8 socket machines getting sold.

Again, I guess that'll end up down to silicon area. If you brought PCIe on to the die, you could drop one HT link straight off, and I guess at that point it's a question of how much you balance the design. You'll need plenty of PCIe lanes for enthusiast platforms (at least 32 for graphics + extras for interconnect to peripherals), so there'll have to be a silicon trade off made at some point.

Although, I seem to remember that you can send DP over PCIe? Perhaps they could do something clever so APUs get display outputs and CPUs get more PCIe lanes?

[DanceswithUnix]

Current FM2 is 20 lanes PCIe for dual x8 and a spare x4. I think the chipset interface is just another x4 of PCIe really as well. Squeezing a few more in does seem advisable.

The 8350 is 315mm^2 die size, Trinity is 246mm^2, so FM2 devices are currently smaller than FX chips.

So, take a Kaveri cpu, snip 3/4 of the shaders off to make some space, add another two cores, fill the rest of the die with L3 cache, add one HT link so you can make a 12 core Opteron part, job done. Fun this armchair CPU architecture isn't it

[DanceswithUnix]

Intel are going to charge $180 for their new mobile CPU??? Blimey, I wouldn't pay that these days for an entire tablet.

http://www.fudzilla.com/home/item/33...es-bay-trail-m

[CAT-THE-FIFTH]

IIRC,AMD has less denser L3 cache than Intel,which is why their CPUs are not that small.

Having said that 53% of Kaveri is not the IGP,so that should be around 127MM2 including chipset functionality. So on 28NM with L3 cache and chipset functionality,an SR based 8 core core CPU probably won't be bigger than a PD one IMHO.

[scaryjim]

Intel are going to charge $180 for their new mobile CPU??? Blimey, I wouldn't pay that these days for an entire tablet.

They look like very high end bay trail parts to me: probably destined for cheap "ultrabook" alternatives (i.e. £400+ laptops!). Bay trail atoms are presumably a lot cheaper, since they're meant to go into tablets starting at $199....

EDIT: if AMD can get a decent ULV Kaveri part out, they could utterly own the lower-end mobile space at this rate...

[CAT-THE-FIFTH]

Intel are going to charge $180 for their new mobile CPU??? Blimey, I wouldn't pay that these days for an entire tablet.

http://www.fudzilla.com/home/item/33...es-bay-trail-m

You should have seen some Intel lovers going on how expensive Jaguar mini-ITX motherboards will be,so I wonder whether they will change their tune??

They look like very high end bay trail parts to me: probably destined for cheap "ultrabook" alternatives (i.e. £400+ laptops!). Bay trail atoms are presumably a lot cheaper, since they're meant to go into tablets starting at $199....

EDIT: if AMD can get a decent ULV Kaveri part out, they could utterly own the lower-end mobile space at this rate...

BT for tablets is a different die AFAIK. However,it could be just Intel cratering margins on their tablet SOCs to gain marketshare.

[DanceswithUnix]

AMD want Mantle to work on Linux and Apple.

http://www.phoronix.com/scan.php?pag...tem&px=MTUxMzY

Which implies to me that Mantle currently isn't anywhere close to working under Linux. Still a two tier driver program then despite all the recent brave talk.

[CAT-THE-FIFTH]

AMD want Mantle to work on Linux and Apple.

http://www.phoronix.com/scan.php?pag...tem&px=MTUxMzY

Which implies to me that Mantle currently isn't anywhere close to working under Linux. Still a two tier driver program then despite all the recent brave talk.

Mantle is not even out on PC yet properly!! Windows has far greater marketshare than Linux for PC gaming. Many major games are not on Linux ATM. Give it time first. AMD is right to prioritise the major market first as that is where the money is. They are not made of money as you know.

Nvidia has a massive percentage of the professional market which means,their consumer drivers are a result of serving that market which has more likelihood of Linux and other OSes(they have 80% of that market),and they have plenty of people already working on that. Plus they lost all three consoles,so they want to(for PR purposes),show that they still have a console. AMD is not in the situation. Most of their sales are for platforms running Windows.

Remember this.

Nvidia has 8100 employees. AMD has under 10000 ATM.

Intel has around 105000.

AMD competes in a far more diverse range of platforms and areas than Nvidia does. It is amazing they do so much with the people they have IMHO.

They have to get momentum on an established platform first with devs. Its news when a big title comes to Linux,that is how poor the state of Linux ports is ATM.

I would do the same. The fact that they are going to bring it to other platforms is news anyway.

[DanceswithUnix]

If you develop a multi platform API on a single platform, then you end up with a single platform API. There will be mistakes, and once you have users of the API those mistakes are locked in.

Heck, even Microsoft got this right. They developed Windows-NT on MIPs CPUs with x86 as second target to make sure they didn't get locked into an x86 only model.

It would just cost one decent dev to fix this, I'm sure Valve would loan one or two.

Disappointed.

[DanceswithUnix]

Nvidia have a fake software only unified memory.

http://www.anandtech.com/show/7515/n...emory-for-cuda

Sounds like it won't help performance, but if it makes code easier to write then that is a step in the right direction.

[scaryjim]

More interested that nvidia are going to be trying to offer unified memory addressing in hardware with their next gen part. Real question is what software support for it will be like. If they limit it to CUDA then all they're doing is seeking a nother way to lock people in the nvidia party. I believe NV aren't involved in the HSA Foundation, which presumably means they're either looking at market fragmentation and customer lock-in, or they're going to simply piggyback on the work of the foundation to create their own approach to unified memory and HSA. Which would seem foolish, tbh, as that would essentially shut them out of the standards develpoment...?

[CAT-THE-FIFTH]

I do like it when Hans de Vries posts on any forum:

http://forums.anandtech.com/showpost...4&postcount=54

He has been around on tech forums for years and has a very good technical knowledge due to his background.