AMD - Piledriver chitchat

[scaryjim]

32MB ESRAM should hold a 1080p image (No MSAA) at 60Hz IIRC.

A 1080p image @ 32bpp with no compression is just shy of 8MB, so 32MB ESRAM would hold 4 frames. If they went 24bpp they could tweak out another frame. If they're compressing the frames, or limiting the absolute colour gamut to significantly less than "full colour", they could potentially push a lot more frames (e.g. 10bpp I think would allow a full 60 frames?). Seems like a waste of ESRAM though, just being used as a frame buffer? You'd expect some cunning pre-loading of textures or polygon data to speed up the rendering.

The other thing that strikes me is that nothing about that block diagram states the northbridge, southbridge, CPU and GPU are separate bits of silicon. That could very easily be an SOC, or an APU + southbridge. The GPU and CPU both clearly access memory directly through the northbridge, which is very APU-like. We could even be seeing more moves towards HSA there, if the GPU is using x86-style memory addressing. Perhaps that's how it can run well with limited bandwidth?

[Terbinator]

3.5GB seems like an awful overhead for a games console, even if it does double up as some sort of media centre.

I wonder if the eDRAM package has any logic on-board, like the 360 one? On that subject, I wonder if that was made with just a few metal layers i.e logic added to RAM, or RAM made on an expensive logic process?

That block diagram looks possible but it still doesn't seem quite right/something missing. It's already been near-confirmed by a few websites, including leaked MS documents, that the next Xbox will use POWER, ARM or x86, so it wouldn't surprise me if it's not completely accurate. I wonder how this ties in with the Xbox Surface, the reported specs of which seem a bit odd, but are on a supposedly official MS document?

The ones from 2010?

The leaked alpha specs had an octo-core x64 CPU too (Xeon, i believe).

If ARM/other is being used maybe they want to keep it off the record for now, especially if its security related?

[DanceswithUnix]

Unless MS are fabbing their own octo-core then it will be a MCM at no native octo-jaguar exists/is planned AFAIK.

I don't see Microsoft worrying about having custom silicon created, and Jaguar is a synthesizable core so they could have as many as the want.

[DanceswithUnix]

A 1080p image @ 32bpp with no compression is just shy of 8MB, so 32MB ESRAM would hold 4 frames. If they went 24bpp they could tweak out another frame. If they're compressing the frames, or limiting the absolute colour gamut to significantly less than "full colour", they could potentially push a lot more frames (e.g. 10bpp I think would allow a full 60 frames?). Seems like a waste of ESRAM though, just being used as a frame buffer? You'd expect some cunning pre-loading of textures or polygon data to speed up the rendering.

The other thing that strikes me is that nothing about that block diagram states the northbridge, southbridge, CPU and GPU are separate bits of silicon. That could very easily be an SOC, or an APU + southbridge. The GPU and CPU both clearly access memory directly through the northbridge, which is very APU-like. We could even be seeing more moves towards HSA there, if the GPU is using x86-style memory addressing. Perhaps that's how it can run well with limited bandwidth?

Possibly the ESRAM is very wide and hence fast, helping bandwidth issues.

[watercooled]

A 1080p image @ 32bpp with no compression is just shy of 8MB, so 32MB ESRAM would hold 4 frames. If they went 24bpp they could tweak out another frame. If they're compressing the frames, or limiting the absolute colour gamut to significantly less than "full colour", they could potentially push a lot more frames (e.g. 10bpp I think would allow a full 60 frames?). Seems like a waste of ESRAM though, just being used as a frame buffer? You'd expect some cunning pre-loading of textures or polygon data to speed up the rendering.

The other thing that strikes me is that nothing about that block diagram states the northbridge, southbridge, CPU and GPU are separate bits of silicon. That could very easily be an SOC, or an APU + southbridge. The GPU and CPU both clearly access memory directly through the northbridge, which is very APU-like. We could even be seeing more moves towards HSA there, if the GPU is using x86-style memory addressing. Perhaps that's how it can run well with limited bandwidth?

Maybe interposers? Separating the dies would improve yield and using an interposer would overcome the bandwidth/latency problems with a ton of separate parts. Now you mention it, 4+ separate packages doesn't seem right for a console. Bonaire plus 8 Jaguar cores+cache would probably mean a >200mm^2 die size at 28nm.

@Terb: This one: http://www.google.co.uk/url?sa=t&rct...41248874,d.d2k

[DanceswithUnix]

Some pics of the inside of the trinity based Valve "piston" PC showing how it goes together:

http://www.brightsideofnews.com/news...ster-play.aspx

[watercooled]

Interesting post, but based on what Xi3 listed on their Kickstarter page, I think they're planning on using the embedded R series APUs rather than desktop sockets as that article suggests, and it makes more sense considering the power envelope and form factor.

But it got me thinking, I wonder if this modularity could be a potential workaround for Intel's rumoured scrapping of sockets? In theory, you could just swap out the CPU daughterboard. Of course, price, availability and openness would be important factors.

[kompukare]

But it got me thinking, I wonder if this modularity could be a potential workaround for Intel's rumoured scrapping of sockets? In theory, you could just swap out the CPU daughterboard. Of course, price, availability and openness would be important factors.

If standardised, why not? The middle part would in effect be the mobo and CPU and the other parts would be re-useable. Seems to recall something like this was possible with of the Workstation buses in the 1980s (maybe VMEbus?).

The middle board would basically be a mini SOC mobo and while it does nothing for IT obsolescence at least when upgrading most parts could be re-used. Unfortunately IT is becoming more throwaway rather than less.

[watercooled]

It's been that way for ages now, 10 or 20 years ago, electronics used to be serviceable, had service manuals etc. Now, if something breaks, it gets binned and replaced. It is partly attributed to miniaturisation though, when you're dealing with tiny SMD components on a tightly packed, multi-layer PCB, there's not much room spare for sockets/test points/etc.

It would be better if even lower-value electronics were recycled properly, disposable tech wouldn't be as much of an environmental problem then. At least in this case, the replaced board is only very small vs an ATX board.

[DanceswithUnix]

Hmm, time for Asrock to come out with another funky motherboard design perhaps. They have done ones with cpu upgrade daughter cards in the past where cpu socket and a couple of dimm sockets went on a plug in card.

Anyone remember the Abit one that would take slot or socket P3 processors?

[CAT-THE-FIFTH]

https://twitter.com/AMDGaming/status/293908415351238657

[CAT-THE-FIFTH]

The AMD server roadmap indicates that AMD is releasing some high performance CPUs in 2014:

http://semiaccurate.com/forums/showp...&postcount=848

Also,do you remember that picture of an AMD CPU with stacked RAM,well here is a document with higher resolution picture:

http://www.i-micronews.com/upload/Ra...ample_2012.pdf

It is an AMD demonstration chip made by GF.

It also appears the company working with Sony and AMD has listed the application as a games console:

http://i.imgur.com/I634RfM.jpg

So it appears,not Intel has experience with using interposers.

[watercooled]

Interposers seem very possible on the consoles IMO.

[Terbinator]

http://phx.corporate-ir.net/phoenix....795&highlight=

AMD revenue $5.42 billion, down 17 percent year-over-year

How???

[CAT-THE-FIFTH]

http://phx.corporate-ir.net/phoenix....795&highlight=


How???

http://forums.hexus.net/general-cons...ml#post2795685

[CAT-THE-FIFTH]

Great article:

http://www.pcper.com/reviews/Shows-a...de-Sea-Islands

Kabini has a 20% IPC improvement over the previous CPUs.

So it seems the IGP in Richland has a new arrangement which is more efficient and the core has a slight IPC improvement too. It appears Trinity supports PCI-E 3.0 but this was not activated in the chips, and the reason why the CPUs were moved to FM2 was for future PCI-E support on the platform.

Kaveri is being introduced to desktop first and AMD is trying to release as soon as possible and hopefully before the end of the year.

Some more details about Richland:

http://translate.google.com/translat...pus-genannt%2F

http://translate.googleusercontent.c...PgWXeBtka-v08w

It looks like the 65W TDP A10 6700 should be faster overall than a 100W TDP A10 5800K.