C2D Overclocking Guide for Beginners

[Clunk]

54/52 is fine, completely normal.

[[GSV]Trig]

lol stopped one and now its 51.43..
Will change the affinity the otherway in a mo and get it warm the other one...

[john87]

i am wondering about theese new c2d's thats coming this summer.. they have a FSB on 1333, but how does that really help? because it is the FSB that determines the speed of the cpu, right? so.. well.. im not really sure what im asking for, im just a bit confused should i wait and get a board that can reach 1333? isnt that just like overclocking..?

[john87]

a hah, i think i get it.. with the higher fsb, the new proceccors, with the same mulitplier, gets a higher core speed.. but, if you put a new c2d on a mobo with a lower fsb, then you would not get the speed you should get..? i am looking at the p5b now, and i cant see any rated fsb speeds.. am i all lost here?

[john87]

i was going through the guide again, and read over.. so, with theese new FSB speeds, the e6600 would be a 3ghz instead of a 2,4? 9 x 333mhz fsb.. i think im getting it now.. but what i dont understand is, why are there coming new c2d proceccors, isnt it just the mobo that gets the extra upgrade?

(sorry about all the posts )

[Clunk]

As far as the FSB is concerned, all that will be different is that instead of the default being 266.6mhz, it will be 333.3mhz. 333.3 mhz quad pumped = 1333fsb.

Currently, its not too hard to make existing c2d chips hit 1333fsb, simply by raising the fsb to 333, most decent motherboards will let you do this.

[Clunk]

Have a google of intel penryn, that should explain further about the new cores

[aidanjt]

Have a google of intel penryn, that should explain further about the new cores

Speaking of which, the thing I find odd is that Intel use the same volume of L1 data cache as L1 code cache, since Intel started the movement towards SIMD instruction sets I would have expected they would have at least twice the L1 data cache so the data buffering can keep up with the flow of instructions with less data cache misses.

[Clunk]

Speaking of which, the thing I find odd is that Intel use the same volume of L1 data cache as L1 code cache, since Intel started the movement towards SIMD instruction sets I would have expected they would have at least twice the L1 data cache so the data buffering can keep up with the flow of instructions with less data cache misses.

I'm not sure that will help him understand

[aidanjt]

I'm not sure that will help him understand

It wont I guess, just thinking out loud

[Harkin]

Speaking of which, the thing I find odd is that Intel use the same volume of L1 data cache as L1 code cache, since Intel started the movement towards SIMD instruction sets I would have expected they would have at least twice the L1 data cache so the data buffering can keep up with the flow of instructions with less data cache misses.

I lost u at code, have to take sum headache tabs now

[john87]

i read at about the penryn family here on hexus, and i fairly got the points i think.. but arent there coming new c2d this summer aswell, with the 1333 fsb? typically named e6650, e7650?

[Clunk]

Yes, I'm not 100% sure on the correct details, but if they are based on the conroe core, they will be the same, but with 333 (1333fsb) instead of 266(1066fsb).

[[GSV]Trig]

Mines been sat at 1333 for just over 24hrs now running Orthos while I've been out, seems fine...

[daza]

Mines been sat at 1800fsb for the past week nah nah, Right anyway my question do these temps look ok to you lot or is there a bad bond somewhere: E6400 at 450x8 @ 1.46 Idles around 45c and loads at 55c ish happy for it to go to 65c if it needs as Im after a E6240 if this one pops it clogs.

(Yes it watercooled)

[Clunk]

Those temps look fine to me, now if I could just sort my own out