AMD - Zen chitchat

[CAT-THE-FIFTH]

Slides from the event are here:

https://www.amd.com/en/events/next-horizon

[krustylicious]

8c/16 per ccx as well, which means if the its 8 zen 2 cores (16c/32t per zen2 core) plus one iox its 128c/256t

intel is doomed in the server space

[watercooled]

Aye, AdoredTV was right about the chiplets!

As for my own predictions: https://forums.hexus.net/cpus/371038...ml#post4023374

WRT the Zen2 core - what's everyone's predictions of the 'low-hanging fruit' AMD spoke about? I'm guessing Fabric speed/latency, AVX width, maybe changes to L3 from victim to inclusive with prefetchers if they think it's worthwhile? Obviously there are likely to be a load of other changes besides, but they seem like obvious targets, and while it was IMHO quite sensible to give AVX width a lower priority on the first generation core, the new node will buy them transistors to compete with Intel in that particular area. Overall the core seems like a very good, well-balanced one (from my understanding anyway) and has plenty of strengths vs competition as-is.

At a higher level, maybe they'll increase the number of cores per cluster?

I started the stream a bit late and it cut out a couple of times so I missed some details, but it looks like they have increased FMA throughput (fairly obvious low-hanging fruit especially given its datacentre target), and they've mentioned cache/prefetchers but haven't gone into that much detail AFAIK. I wonder if L3 has been the main area of improvement. They've also, assuming I've interpreted it correctly, increased CCX size to 8 cores?

I do sorta wonder how this translates to a desktop CPU though, how many cores per chiplet, etc?

[CAT-THE-FIFTH]

The chiplet is probably going to be under 80MM2!! The yields should be great and it should lower costs.

Edit!!

Also AMD can use GF to make the controller chips and TSMC the chiplets.

WSA and high performance sorted!!

[krustylicious]

I do sorta wonder how this translates to a desktop CPU though, how many cores per chiplet, etc?

Likely to be one zen2 chiplet (16c/32t) and one iox. It does take a while to sink in what they have done. Removing identical IF from each zen core and moved that to separate chip meant that, reduced space per chiplet, also rumoured is the that IF doesn't scale well to 7nm(so stays in 14nm) that should mean higher clocks. Also higher clock count, and in theory go above 8 zen cores.

In another words stupidly scaleable

Plus with the io separate, it means they can do different io chips for each segment: desktop/datacentre/gaming etc ..

[krustylicious]

The chiplet is probably going to be under 80MM2!! The yields should be great and it should lower costs.

Edit!!

Also AMD can use GF to make the controller chips and TSMC the chiplets.

WSA and high performance sorted!!

we could see 5ghz ryzen 3000 series ..

I'm still loving how intel has been completely wrong footed and a number of jurnos getting the chiplet, the 8+1 die count on the eypc cpu right and also the 8ccx but not putting everything together.

[watercooled]

Hmm, having a smaller die helps with clock distribution too. And yeah I guess the io chip is sorta an on-package Northbridge - just make a few different versions for each market, as required?

Or, another option would be to integrate GPU with an 8 core CPU and target that at everything on desktop but the Threadripper HEDT market. It seems like you wouldn't save much die space dropping to 4C for APUs (plus would throw a spanner in the works for having to design another, smaller CCX module), though I guess power would be a potential concern. Then again, not making use of the chiplet on desktop seems like a lost opportunity too! Or maybe the integrated GPU will end up being another chiplet? Lots of possibilities!

8 core CCX potentially helps with the IF latency stuff in games regardless of any IF improvements too, and jumps right to Intel's 8 core 'module' in terms of latency consistency.

[krustylicious]

just remember the IF stuff is now on the seperate io chip. The latency for two chiplets should be the same for 1.

[krustylicious]

Just to point out that chiplets is as revolutionary as x64 and dual core

[krustylicious]

Hmm, having a smaller die helps with clock distribution too. And yeah I guess the io chip is sorta an on-package Northbridge - just make a few different versions for each market, as required?

Or, another option would be to integrate GPU with an 8 core CPU and target that at everything on desktop but the Threadripper HEDT market. It seems like you wouldn't save much die space dropping to 4C for APUs (plus would throw a spanner in the works for having to design another, smaller CCX module)

They should be able stitch the vega die via IF and iox chip, which should mean an 8 core and 4 core apus next yeah. Might be able to do 12c apu. Depends on the power delivery of the am4 socket.

[watercooled]

just remember the IF stuff is now on the seperate io chip. The latency for two chiplets should be the same for 1.

I was more on about inter-core communication if you're responding to my post.

They should be able stitch the vega die via IF and iox chip, which should mean an 8 core and 4 core apus next yeah. Might be able to do 12c apu. Depends on the power delivery of the am4 socket.

The thing is, 4C/12C would mean another CCX design unless a hypothetical 4C design was actually an 8C design in silicon with some cores disabled for yield/power reasons.

Yet another option could be GPU on the iox, though that would limit them to 14nm so probably not. Reminds me of Clarkdale though!

[krustylicious]

ahh i'm wrong - 8c x 8 dies

[pp05]

On my ITX mobo cpu it has 8 pin for cpu. my previous only had 4. If your psu only has 1 x 4 pin cable for cpu will it still run the system?

[CAT-THE-FIFTH]

02:32PM EST - 8 cores per Zen 2 die

02:33PM EST - Cray benchmark: One socket Rome scored 28.1 seconds, Two 8180M 30.2 seconds

02:33PM EST - Rome air-cooled, non-overclocked, not final frequency

02:34PM EST - On track for 2019

[CAT-THE-FIFTH]

A closer look:

https://www.anandtech.com/show/13561...64-zen-2-cores



Two chiplets look smaller than a Ryzen CPU or APU!!

[watercooled]

Hmm, I might have a go at pixel-counting the die size if no-one beats me to it!

Looks like 8 cores per chiplet then, but I wonder if there's any significance to the chiplets being paired up like that?

Edit: Well I went and did it. The lines aren't too sharp in the photos I can find so allow some tolerance but I got ~75mm2 for a chiplet (of which there are 8). That's based on TR4/SP3 socket dimensions.